The present invention generally relates to semiconductor devices and more particularly to the fabrication process of a semiconductor device having a multilayer interconnection structure.
In modern semiconductor integrated circuit devices, a large number of semiconductor elements are formed on a common substrate and a multilayer interconnection structure is used for connecting these semiconductor elements with each other.
In a multilayer interconnection structure, interlayer insulation films are laminated one another, wherein each interlayer insulation film is embedded with an interconnection pattern forming an interconnection layer. Thereby, an upper interconnection layer is connected to a lower interconnection layer by way of a via-contact formed in the interlayer insulation film.
With recent ultrafine and ultra high-speed semiconductor devices in particular, a low dielectric constant film (so-called low-K dielectric film) is used for the interlayer insulation film together with a low-resistance Cu pattern that forms the interconnection layer in the prospect of reducing the problem of signal delay caused in the multilayer interconnection structure.                Patent Reference 1 Japanese Laid-Open Patent Application 2-62035 official gazette        Patent Reference 2 Japanese Laid-Open Patent Application 2003-218198 official gazette        Patent Reference 3 Japanese Laid-Open Patent Application 2005-277390 official gazette        Patent Reference 4 Japanese Laid-Open Patent Application 2001-326192 official gazette        Patent Reference 5 Japanese Laid-Open Patent Application 11-54458 official gazette        Patent Reference 6 Japanese Laid-Open Patent Application 5-102318 official gazette        